FPGAs Development Tools Setup

• Quartus Download and Install

• How To Setup a Quartus Project (New Project Wizard)

• How To Simulate with ModelSim

• How To Simulate with Quartus ModelSim-Altera

• How To Simulate with EDA Playground

Quartus Prime

Quartus Download and Install - Windows

1. Get Quartus Combined Files .tar and extract it. Make sure to select the right version and edition for you
2. Run the .bat file for your edition for example setup.bat for lite edition, this will start the installation wizard
3. Select Installation destination directory (use default, avoid adding spaces), this will take a while so grab a beer or something
4. Select Yes when prompted to install drivers and select "Run Quartus Prime Software" when prompted for license

Use Download manager tool, direct download may result in a corrupted download that could cause problems during installation

How To Setup a Quartus Project (New Project Wizard)

1. Go to File -> New Project Wizard

2. Set working directory and top-level entity name

• Create a folder and set it as working directory or give a path that does exist and Quartus will create a folder for you, this is where your Quartus project file .qpf will be stored so if you don't create a directory or give a path the files will be stored exactly in that path
• Set top-level entity name, this name should match source code file top-level Verilog/SystemVerilog module

3. Select Empty Project

4. (Optionally) Add extra source files, usually as .v, .sv source files or as a library (path to .v and .sv files) and IP modules as .qip files)

5. Select device from Available Devices list. You can specify characteristics to filter such as:

• Family - E.g. Cyclone V (E/GX/GT/SX/SE/ST)
• Devices - E.g. Cyclone V GX Extended Features
• Package - E.g. FBGA
• Pin count - E.g. 672
• Speed grade - E.g. 7_H6

6. Click Skip in EDA Tools settings (if you plan to simulate you can set the simulator here or do it later check How To Simulate with Quartus ModelSim-Altera for more info) finally review setup and click Finish

7. Create/Add the sources code files of your project, usually in a /src dir. created in project folder or all the sources directly in the project.

• In the project directory create a .v/.sv file with the same name of the top-level name give in step 2 and add it to the project. For this you can:
  • Use Quartus to create a file with File -> New, select Verilog HDL File / SystemVerilog HDL File, click OK, write the module code there (module name must be the same as top-level), click Save and make sure the Add file to current project box is checked
  • Create v/.sv a file in the project directory with the module's code (module name must be the same as top-level) and add it to the project with Project -> Add/Remove Files In Project...

8. To check everything is OK you can right-click in Analysis and Synthesis and select Start, this should complete successfully (maybe few warnings)

9. You can now build your project using the Start Compilation Button, the process should complete without errors, you may get warnings due to pin placement and timing requirements since we didn't set up a constraints file but if you only want to simulate your design you can ignore this

ModelSim

• General ModelSim Considerations:

  • Make sure your TestBench has a timescale directive `timescale 1ns/1ns
  • Make sure your TestBench has a $stop directive E.g. $display($time, "<< Simulation Complete >>"); $stop;
  • To add signals browse through the modules list using the Sim window pane, select a module and in the Objects window pane select the signals right-click -> Add to -> Wave to add signals
  • Restart a simulation: Simulate -> Restart... click OK then Simulate -> Run -> Run -All

• For Standalone ModelSim you can download the .exe from the Download Center for FPGAs, you don't need to download and install other tools, only select the ModelSim-Intel FPGA Edition (includes Starter Edition)

How To Simulate with ModelSim

1. Create a folder with your .v/.sv files, your module to test and testbench files. E.g. Counter.sv and Counter_TB.sv

2. Open ModelSim and go to File -> New -> Project...

• Give it a Project Name. E.g. ModelSimTest or Counter
• Change Project location to the folder with your files. E.g D:/ModelSim/ModelSimTest

3. A window will show up click on Add Existing File, select your .v/.sv files and click OK

4. Compile files by going to Compile -> Compile All or right-click and Compile All

5. In the "Library" Tab expand the work library right-click on your testbench module name (E.g. Counter_TB) and select Simulate

6. Add signals to wave (right-click -> Add to -> Wave) and then click on Simulate -> Run -> Run -All

How To Simulate with Quartus ModelSim-Altera

1. Setup a Quartus project and set ModelSim in Tools -> Options > EDA Tool Options in the ModelSim-Altera field set path to ModelSim E.g.: C:\intelFPGA_lite\17.0\modelsim_ase\win32aloem

2. Setup EDA Tools Settings

3. Go to Assignments -> Settings -> EDA Tools Settings in the Simulation section select Tool Name: ModelSim-Altera and Format(s): SystemVerilog HDL

4. In the NativeLink settings section, select the Compile test bench option, and then click the Test Benches... button. On the opened window click on New...

5. Set Test bench name and Top level module in test bench fields (Make sure the names in your test bench file match with that top level module name here), for example: - Test bench name: E.g. CounterFlagSyncResetEnable_tb - Top level module in test bench: E.g CounterFlagSyncResetEnable_tb

6. Under the Test bench and simulation files you will need to add your test bench HDL file, create one in your project and use the Add button to add it, for example: CounterFlagSyncResetEnable_tb.v and click OK

7. Click OK in Settings window and build your project (Start compilation). Make sure EDA Netlist Writer step completes without errors

8. Run Simulation using Tools -> Run Simulation Tool -> RTL Simulation this should open ModelSim with your simulation

How To Simulate with EDA Playground

1. Go to EDA Playground and create an account, you can use Google account to avoid verification

2. Setup HDL Language and Simulator for example:

• Testbench + Design select SystemVerilog/Verilog
• UVM / OVM set to None
• Dont need to select anything in the Other Libraries section
• Tools & Simulators select Icarus Verilog 0.9.7 and check Open EPWave after run option

3. Add your files in the testbench.sv and design.sv sections. For example:

• design.sv:

  `default_nettype none
  module Register
  #(
    parameter Word_Length = 8
  )
  (
    input  clk,
    input  reset,
    input  [Word_Length-1:0] Data,
    output [Word_Length-1:0] Q
  );
  
    reg [Word_Length-1:0] Q_reg;
  
    always@(posedge clk or negedge reset) begin
      if (reset == 1'b0)
        Q_reg <= 0;
      else
        Q_reg <= Data;
    end
  
    assign Q = Q_reg;
  
  endmodule
  

• testbench.sv:

  `default_nettype none
  module tb;
    localparam nbits = 16;
    reg [nbits-1:0] d;
    reg clk, rst;
    wire [nbits-1:0] out;
  
    Register #(
      .Word_Length(nbits)
    ) dut(
      .clk(clk),
      .reset(rst),
      .Data(d),
      .Q(out)
    );
  
    initial
      begin
        $dumpfile("dump.vcd");
        $dumpvars(0, dut);
        clk = 0; rst = 1; d = 16'hAAAA;
        #1 rst = 0; #3 rst = 1;
        #4 d = 16'hBBBB; #4 d = 16'hCCCC;
        #4 $finish;
     end
  
    always
      begin
        #1 clk<=~clk;
      end
  
  endmodule
  

4. Save your design and Run it

EDA Playground does NOT support SystemVerilog for simulation

References

• How to Simulate and Test SystemVerilog with ModelSim
• Simulation Quick-Start for ModelSim
• Become an FPGA Designer in 4 Hours